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EECS151 Tapeout logo

EECS151 Tapeout

Lecture: Fri, 3:00–4:30 PM, BWRC

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Week 0 Announcements

Aug 22
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  • The first lecture is on Friday, September 12.
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Past announcements

Course Calendar

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Wk. Date Lecture Labs Project Deliverable
0 Fri
Sep 05
0. Sign up for the Decal! To avoid dead links, see the forms above. We start a week later than standard classes.
1 Fri
Sep 12
1. What does it mean to tapeout a chip? Intro to the class, tapeouts, and the flow needed to get there! Lab 0, 1A, 1B
(due Fri Sep 26)

Practical introduction to Git and Chisel. Test instructional account and Chipyard setup.
Get to know your potential collaborators!
2 Fri
Sep 19
2. Introduction to SoCs and their Parts + Chipyard. Introduction to SoCs and their various parts using Berkeley’s Rocket Chip - an SoC generator. Lab 2 (A, B, C, optional: X)
(due Fri Oct 03)

Practical Chipyard intro. Step by step integration of EECS151 RISC-V core.
Make sure you have access to your (functional) EECS151 CPU - if yours has issues, make some friends!
3 Fri
Sep 26
3. SoC Interconnects, Protocols, and More Chipyard. Figure out how SoC parts are interconnected and what that looks like in Chipyard (TileLink, Configs..). Lab 3
(due Fri Oct 10)

Chipyard exploration to motivate starting own side projects.
Evaluate your status and form teams by next week. Decide if want to do a side project.
4 Fri
Oct 03
4. SoC Peripherals If OFO Tile works, work on side project - submit by next week a proposal and timeline.
5 Fri
Oct 10
5. Surprise! (Stay tuned~) :3 Heat of side project work starts, for those doing that.
6 Fri
Oct 17
6. Midterm Student Presentations. Make sure we’re _all_ on the same page regarding who’s aiming to do what before RTL Freeze. Side project option - by RTL freeze should be confident in the functionality of the system.
7 Fri
Oct 24
7. **RTL FREEZE** The big RTL & verification rush!
8 Fri
Oct 31
8. SoC Verification Lab 4
(due TODO)

Practical experience verifying OFO Tile and side project.
RTL done!
9 Fri
Nov 07
9. An Introduction to Physical Design
10 Fri
Nov 14
10. Physical Design Applied: *.tcl Tour Lab 5
(due Due on tapeout deadline (prioritize tapeout if you're working on it) )

Practical experience running PD. Preliminary numbers for projects.
Initial Physical Design
11 Fri
Nov 21
11. Final Student Presentations / Design Review
12 Fri
Nov 28
12. Tapeout Deadline!!!!! TODO: FIX DATES Tapeout Deadline!!!
13 Fri
Dec 05
13. Thanksgiving Break - No Meet Document what you've done! Final feedback form.
14 Fri
Dec 12
Fill out staff interest form!
15 Fri
Dec 19
HW5