EECS151 Tapeout (aka 151T, aka “The Tapeout Decal”)

EECS151 Tapeout is a Decal (student-run course) giving a hands-on, end-to-end experience in SoC design and implementation culminating in a tapeout. Learn more on the Course Info tab!

  • [After Feb 3, email us] Enroll for Spring 2025 here!

  • Lecture: Mondays 3-5pm in BWRC. Ring the doorbell to be let in! We will meet in the big central room.

  • You will find labs and project repositories on our Github.

  • When in doubt, ask on the Discord: berkie.ee/151t-discord.

  • You can also email us at 151tapeout@ieee.berkeley.edu.

No matter what, don’t forget to have fun! :3

From Lucy & Elam, your 2024-2025 staff.

Spring Schedule

Pardon our dust! The course is always improving and the links below might not be most up to date.

Note that this schedule is subject to change. All updates will be posted on Discord.

WeekTopicReferenceLabLab DueProject Deliverable
0
1/27		 Sign up for the Decal!

To avoid dead links, see the forms above. We start a week later than standard classes.
1
2/3		 What does it mean to tapeout a chip?

Intro to the class, tapeouts, and the _flow_ needed to get there!		 Slides Folder Labs 0, 1A, 1B

Practical introduction to Git and Chisel. Test instructional account and Chipyard setup.		 In two weeks. Get to know your potential collaborators!
2
2/10		 Introduction to SoCs and their Parts + Chipyard

Introduction to SoCs and their various parts using Berkeley’s Rocket Chip - an SoC generator.		 Slides Folder Lab 2 (A, B, C, optional: X)

Practical Chipyard intro. Step by step integration of EECS151 RISC-V core.		 In two weeks. Make sure you have access to your (functional) EECS151 CPU - if yours has issues, make some friends!
3
2/17		 President's Day - No Class

We will do our best to host an alternative or OH, stay tuned!
4
2/24		 SoC Interconnects, Protocols, and More Chipyard

Figure out how SoC parts are interconnected and what that looks like in Chipyard (TileLink, Configs..).		 Slides Folder Lab 3

Chipyard exploration to motivate starting own side projects.		 In two weeks. Evaluate your status and form teams by next week. Decide if want to do a side project.
5
3/3		 SoC Verification

Learn what it means to “verify” an SoC, with Rocket Chip as an example, in research and industry. Figure out how to scope your project to match your pace.		 Slides Folder Lab 4

Practical experience verifying OFO Tile and side project.		 In two weeks. If OFO Tile works, work on side project - submit by next week a proposal and timeline.
6
3/10		 Surprise! (Stay tuned~)

:3		 Slides Folder Catch up on outstanding work. Get "PD ready". Presentations next week. Heat of side project work starts, for those doing that.
7
3/17		 Midterm Student Presentations

Make sure we’re _all_ on the same page regarding who’s aiming to do what before RTL Freeze.		 Slides Folder OFO Tile option - by RTL freeze should be confident in the functionality of the system. Side project option - by RTL freeze should be confident in the functionality of the system.
8
3/24		 Spring Break -> **RTL FREEZE**

The big RTL & verification rush! **RTL FREEZE is Sunday 3/30, end of spring break (or realistically - Monday 3pm 3/31).**
9
3/31		 PD at a High-Level

Learn what “integration” truly means - in our complex, physical world..		 Slides Folder Lab 5

Practical experience running PD. Preliminary numbers for projects.		 In a week. DRC/LVS-clean GDS in two weeks!
10
4/14		 **TAPEOUT DEADLINE**

Whatever it takes to be "done" - that means DRC/LVS-clean GDS.		 ..BE DONE BE DONE BE DONE..
11
4/21		 Final Student Presentations

Tell us your final results!		 Slides Folder
12
4/28		 Post-Tapeout: Fabrication and Next Steps

Understand at a high level what’s going to happen to the design once it’s “sent out.” Have some idea of next steps, be it classes to take or projects to tackle.		 Slides Folder Document what you've done! Final feedback form.
13
?/?		 RRR Week - No Meet

14
?/?		 Finals Week - No Meet

Good luck!		 Fill out staff interest form!