Course Info
EECS151 Tapeout is a Decal (student-run course) giving a hands-on, end-to-end experience in SoC design and implementation culminating in a tapeout.
Students with a background in the fundamentals of digital design and VLSI CAD tools (EECS151 + ASIC lab) will learn how to use the Chisel hardware description language and Chipyard (an agile hardware design framework) to integrate their EECS151 ASIC core or a custom IP block of their own design into a full-scale System-on-Chip (SoC). While covering the basics of agile SoC design concepts and methodology, the course is primarily a hands-on experience. One (or more, depending on student interest) class SoCs are planned to be taped out in the open-source Skywater 130nm process at the end of the semester. Extra chip area is available for motivated students with unique, large-scale projects.
The course aims to give all students hands-on experience in every step of the SoC design process from system-level design (interfaces, modular decoupling), to toplevel integration and physical design with commercial CAD tools though Berkeley’s Hammer tool. Students will participate in a class project consisting of one or more physically realized and fabricated SoCs in the open-source Skywater 130nm process node. Student contributions to the designs may range from a chipyard-integrated version of their EECS 151 ASIC core to custom accelerators or off-chip peripheral interfaces. It is emphasized that while multiple students may collaborate on a single SoC (or even within a module), every student will receive hands-on experience with the full tapeout process, from system architecture to GDSII signoff.
This course spans 13 weeks. Class meets for two hours once a week. Each class will generally consist of a short mini lecture, overview of project status, and check-ins with each team on milestones and obstacles. Students are expected to spend a bit more time each week outside of class time working on their project. The semester will culminate in chip tapeout through Efabless’ chipIgnite, student presentations, and a class poster.
Enrolling in EECS151T
Fill out THIS form to join! Our DeCal listing from Fall ‘24 is https://decal.studentorg.berkeley.edu/courses/7769. More information about enrollment will be sent to those who fill out the enrollment form.
Prerequisites
This rigorous course is designed for students who have completed EECS 151 LA ASIC and/or EE 194/290C (the traditional ‘Tapeout’ and ‘Bringup’ courses). Students who instead completed EECS 151 LB FPGA are welcome but may have a higher learning curve due to less prior experience with ASIC CAD flows. Students who have not completed EECS 151 or Tapeout/Bringup are recommended to take this Decal after having completed the course. Those unsure are welcome to email us. We are extremely welcoming to self-motivated students of various backgrounds but do wish to emphasize that background knowledge will be helpful, especially as this is an early iteration of the course.
Grading
bCourses will be available. We will keep track of grade-related things mostly in Gradescope. Other course content will be found here on the website and on GitHub. When in doubt, ask on the Discord: berkie.ee/151t-discord
Office Hours
We may have work and “office hours” sessions. You can also organize your own work sessions. We will use this calendar to track them.
Class calendar: http://berkie.ee/tapeoutcalendar
Contact
Please email us at 151tapeout@ieee.berkeley.edu